Skewed branch predictors

As modern microprocessors employ deeper pipelines and issue multiple instructions per cycle, they are becoming increasingly dependent on good branch prediction. During the past ve years, researchers have shown that branch-prediction accuracy can be improved by basing predictions on the outcome of previous branches. Many such methods have been proposed, but they all share a common characteristic: they require hardware resources to implement the tables and state machines that record the branch-history information. Because hardware resources are invariably limited, it is not possible to hold all relevant branch history for all active branches at the same time, especially for larger workloads consisting of multiple processes and operating-system code. The problem that results, commonly referred to as aliasing in the branch-predictor tables, is in many ways similar to the misses that occur in nite-sized hardware caches. The rst contribution of this paper is to propose a classiication for three diierent types of branch aliasing (compulsory, capacity and connict). We argue that although previous research has resulted in reductions in compulsory and capacity aliasing, little has been done to reduce connict aliasing. Drawing on established work in caches, our second contribution is to propose the skewed branch predictor, a multi-bank, tag-less structure, designed speciically to reduce the impact of connict aliasing. Through both analytical and simulation models, we show that the skewed branch predictor removes a substantial portion of connict alias-ing by introducing redundancy to the branch-predictor tables. Although this redundancy increases capacity aliasing compared to a standard one-bank structure of comparable size, our simulations show that the reduction in connict aliasing overcomes this eeect to yield a net gain in prediction accuracy. INRIA Pr edicteurs de branchement a redondances R esum e : Avec des pipelines de traitement des instructions de plus en plus larges et profonds, les performances des microprocesseurs r ecents sont conditionn ees par un m ecanisme de pr edic-tion des branchements performant. R ecemment, certains travaux de recherche ont montr e qu'on pouvait am eliorer la qualit e de la pr ediction en se basant sur les directions prises dynamiquement par les derniers branchements. Plusieurs variations de ce principe ont et e propos ees, mais elles ont toutes en commun l'utilisation d'une table de pr edicteurs mise a jour dynamiquement. Comme la taille de cette table est limit ee par le budget mat eriel et le temps de cycle, il n'est pas possible de conserver dans cette …